The invention generally relates to logic gates with complex functions and, more particularly, to such gates presenting essentially no logic signal delay penalty.
Emitter-dots and collector-dots have been very useful in providing simple and fast OR/AND functions in bipolar designs. However, the input signals must be limited to a single fanout. In case of collector-dots, level clamps are generally needed to prevent excessive down levels, and the clamps introduce extra delay penalty. With the ever-increasing scale of chip integration, chip reconfiguration controls become essential for yield, testability and reliability-serviceability-availability. The flexibility of variable logic configurations, however, is at a cost of delay penalties due to the extra control logic, some of which lies in the logic signal path. Consider, for example, the prior art cascode emitter-coupled logic (ECL) selector circuit of FIG. 1. The selector signal CT determines which transistor 1 or 2 of current switch 3 and which current switch 6 or 9 are turned on. Logic signal A determines the conduction levels of transistors 4 and 5 when current switch 6 operates. Similarly, logic signal B determines the conduction levels of transistors 7 and 8 when current switch 9 is turned on.
In operation, selector signal CT is essentially a DC control signal and, therefore, need not be applied to a circuit having an extremely short response time. Thus, the relatively slow switching time of current switch 3 is largely irrelevant and can be tolerated in many common applications. The same is not true of the signal pathways for rapidly changing logic signals A and B. Here, fast, substantially zero signal transfer delay is desired from the respective input terminal to shared output terminal 10. It will be noted, however, that current switch 6 lies within the signal pathway of logic signal A whereas current switch 9 is in the path of logic signal B. The result not only is a delay (tolerable) in the control signal response but also similar delays (objectionable) in the logic signal responses. The delays from any of the inputs A, B, or CT to the output (10) are typically about 100 picoseconds in the advanced bipolar technologies.
Attempts have been made in the art to reduce the delay encountered in logic circuits due to transistor switching. "Speed-up" or "overdrive" capacitors have been added to switching circuits to force transistors to switch more rapidly. Examples of such techniques are disclosed in U.S. Pat. No. 4,306,159 issued to Siegfried K. Wiedmann on Dec. 15, 1981; U.S. Pat. No. 4,605,870 issued to Allan H. Dansky et al. on Aug. 12, 1986; U.S. Pat. No. 4,626,709 issued to Nikhil C. Mazumder et al. on Dec. 2, 1986, and IBM.RTM. Technical Disclosure Bulletin, "Current Switches with Speed-Up Junctions" by R. C. Wong, Vol. 33, No. 4, Sep. 1990, pp. 450-452. Although some improvement is achieved in switching speed by the speed-up capacitor schemes, the limiting factor, i.e., the switching transistor per se, is not eliminated.
Thus, it is desirable to provide the flexibility of variable logic configurations by means of controlled circuits which can be as fast as prior emitter dots without incurring the delay penalties due to the extra control circuits necessary to realize the more sophisticated functions such as, for example, select, exclusive OR and latch.